1. Field of the invention
The invention relates generally to a memory access interface, and more specifically to a memory access interface in which a memory is shared between a micro-controller having an address/data multiplexing bus and a microprocessor
2. Description of the Related Art
In order to reduce the number of I/O pins in some micro-controllers, such as micro-controllers of the 80C32 series, a set of output pins are shared between a data bus and a lower-bit address bus. FIG. 1 shows a typical memory system having a micro-controller and the address/data multiplexing bus. Referring to FIG. 1, the micro-controller 11 utilizes an address latch 12 to latch the lower-bit address signal A7:0 of the address/data multiplexing bus A7:0/D7:0 when the address-latch-enable signal ALE is enabled The address signal A7:0 together with the higher-bit address signal A15:8 are inputted to the address bus of the memory 13. The reading signal/READ of the micro-controller 11 is transferred to the output-enabling control terminal OE of the memory 13 so as to enable or disable the output of the memory 13. When the reading signal/READ is enabled, the output from the memory 13 is also enabled, and the data corresponding to the address signal A15:0 is transferred to the data bus D7:0. The micro-controller 11 accesses the data of the data bus D7:0 of the memory through the address/data multiplexing bus A7:0/D7:0.
FIG. 2 shows a typical timing diagram during the accessing cycle of the micro-controller 11. As shown in FIG. 2, the accessing cycle of the micro-controller 11 is divided into an address phase and a data phase. The address-latch-enable signal ALE is enabled in the address phase, while the reading signal/READ is enabled in the data phase.
Because the memory in the memory system can only be accessed by a single micro-controller, the efficiency of the memory is poor. Therefore, the efficiency of the memory can be improved if two or more microprocessors are capable of sharing the memory.